Clocking is one of the complex aspects in Data Circuit Terminating Equipments also called modems. A DCE requires timing circuits allowing a particular Data Terminal Equipment (DTE) to communicate with another DTE through a telecommunication line.
The DCE must include timing arrangement circuits providing the different clocks that are necessary in the modem and particularly those used at the interchange circuits between the DTE and the DCE. Indeed, according to the V24 CCITT Recommendations (Fascicle VIII.1--Rec. V.24), clocks are to be included in the modems to provide the DTE with transmitter signal element timing on circuit 114 (called `Transmitter signal element timing` circuit) and receiver signal element timing on circuit 115 (called `Receiver signal element timing` circuit). Alternatively, the Transmitter signal element timing may be originated in the DTE instead of in the DCE equipment and be transferred to the modem via an interchange circuit 113. For simplicity, the clocks existing on interchange circuit 115 and interchange circuit 114 are respectively called `Transmit clock` (XC) and `Receive clock` (RC). FIG. 1a illustrates the well known way of generating the receive clock RC provided at the interchange circuit 115 according to the CCITT V.24 Recommendation. Traditionally receive timing signals are provided from an internal oscillator 1 included in the modem and a succession of dividing circuits: a controlled divide-by-(K.+-.1) circuit 2, (which performs a divide-by-(K+1) or a divide-by-(K-1) operation according to the value appearing on its control lead, a divide by M circuit 3, and a divide by N circuit 4. The output of divide by M circuit 3 provides a Receive sampling clock on a lead 7 pulsing an A/D (Analog to Digital) converter 5, for instance a sigma-delta coder. The A/D coder converts the analog signal received on the telecommunication line into a digital PCM information that is transferred to a microprocessor 6. The processor 6 performs an analysis of the converted signal on the line and controls divide-by-(K.+-.1) circuit 2 so that the Receive sampling clock at the output of circuit 3 precisely indicate when the line signal has to be sampled. The Receive clock operates in synchronism with the receive sampling clock. FIGS. 1b illustrates the traditional way of generating an internal transmit clock XC which is then transferred to the DTE via interchange circuit 114 according to the CCITT V.24 Recommendation. The internal transmit clock is generated from internal oscillator 1 through a set of two dividing circuits, resp. a divide-by-Q circuit 9 and a divide by R circuit 10. the output of divide-by-Q circuit also provides a transmit sampling clock on a lead 12 which is used to pulse a D/A (Digital to Analog) converter converting digital PCM information coming from processor 6 (not shown) into an analog signal which is eventually transmitted to the telecommunication line.
It appears from above that the known timing arrangements circuits involve numerous dividing circuits which increases the overall complexity of the modem. The latter complexity is even more increased when considering the new functions that are required in modern DCE: the capability of operating in tailing mode, with synchronous networks, with advanced testing functions such as analog loop, the capability of providing echo cancellation in full duplex modem of the V32 family, data multiplexing on the DTE interface, Error correction procedures described in CCITT V42 requirements.
A modem providing tailing capability is such that the Transmitter signal element timing is originated in the DTE instead of in the DCE equipment and is transferred to the modem via interchange circuit 113. FIG. 1c shows the additional elements that are traditionally added to the circuit of FIG. 1b in order to provide a transmit sampling clock on lead 12 which is slaved on an external clock on interchange circuit 113 which is provided by the DTE. For this purpose, a comparator 14 having an enable lead 13 compares the value of the Transmit clock XC with that of the external clock and according to the result of the latter comparison, comparator 14 controls a controlled divide-by-(P.+-.1) circuit 8 which is inserted between internal oscillator 1 and divide-by-Q circuit 9. When enable lead 13 is set at a high level, comparator 14 creates a feedback loop between the external clock existing on circuit 113 and the transmit clock on circuit 114 thereby entailing the latter to be slaved on the former. On the contrary, when enable lead 13 is set at a low level, comparator 14 and divide-by-(P.+-.1) are disabled what results in the circuit of FIG. 1c operating as that of FIG. 1b.
The complexity of the modem increases more when the latter is intended to be used in synchronous networks, for instance Digital Data Service in the United States of America. A DCE designed to be connected to synchronous networks is such that the transmit clock is slaved on the receive clock. FIG. 2a shows a traditional timing arrangement circuit providing this additional capability with respect to the circuits of FIG. 1c. The external clock 113 and receive clock 115 are transmitted to the two inputs of a multiplexer circuit 15 which, according to the state of its select lead, distributes one of the two latter clocks to the input of comparator 13. Therefore, according to the state of the select lead of multiplexer 15, the transmit clock on lead 114 is slaved on the external clock on circuit 113 or the receive clock on circuit 115. In addition to the complexity of the above timing arrangement circuits required in synchronous modem, a second drawback appears in the prior art solution. Generally for testing purposes, an analog loop may be required in a DCE which entails the switching of the transmit clock on lead 114 from the receive clock to the internal clock. In traditional DCE equipment, that switching results in glitches appearing in the transmit clock which are likely to disturb the transmission between the DTE and its associated DCE equipment.
Another step in the continuous sophistication process of the timing arrangement circuits in DCE equipment came with the insertion of echo cancellation circuits in the modem. High-speed full-duplex data transmission over two-wire lines is of immense practical interest. The techniques for achieving this goal implies echo cancellation techniques. The transmitter and receiver included in the DCE are jointly coupled to a two-wire line via an hybrid transformer. In an environment of changing channel characteristics (e.g. switched network), the hybrid balancing, if fixed, will at best provide a compromise match to the line impedance. In this mode, a vestige of the local transmitted signal, leaking through the hybrid, can be expected to interfere with the received signal from a far-end simultaneously operating transmitter. To remove the interfering echo component, the local receiver must perform echo cancellation, that is, estimate the echo signal and subtract it from the received signal prior to making decisions. In a environment of digital signal processing it is desirable to perform echo cancellation entirely digitally. Therefore it appears that the above mentioned subtraction of the echo component from the incoming signal requires the transmit and receive sampling clocks on leads 12 and 7 to be equal. FIG. 2b illustrates the additional components that are required for providing a receive sampling clock on lead 7 equal to the transmit sampling clock on lead 12. For this purpose an additional multiplexer circuit 16 has two inputs respectively connected to the output of divide-by-M circuit 3 and divide-by-Q circuit 9 and an output providing the receive sampling clock on lead 7. A SELECT lead controls multiplexer 16 by processor 6 (not shown in FIG. 2b), which control results in one of the two signals existing at the output of divide-by-M circuit 3 or divide-by-Q circuit 9 being transmitted to lead 7. The complexity of the timing arrangement circuits increases more when considering the fact that in some cases such as 19200 Bps modems, the ratio bit-time/baud-time traditionally simple becomes complex. For instance, telecommunication equipment knows traditional DCEs provide a 1200, 1600 or 2400 bauds modulation associated with a 4800 bps or 9600 bps transmission. The above mentioned ratio having thus simple values (2 or 4), and the divider circuits involve only a few components. However, the tendency of increasing the use of the bandwith of the telecommunication line entails the utilization of less simple ratio. Such complex ratios inevitably increases the already complex timing arrangement circuits involved in the DCE equipment.
An additional degree in the sophistication process of timing arrangement circuits in the DCE is reached with the V14CCITT requirements in the case when a synchronous DCE communicates with a asynchronous DTE. In such a communication, the DCE which is connected to a asynchronous DTE has to provide the acquisition of the asynchronous character during transmission and the reconstitution of the asynchronous characters during reception with the control of the bit length in order to compensate the DTE and the line data throughput potential difference. Indeed, the data to be transmitted at the DTE interface by the DCE may have a higher throughput than that of the line throughput. In that case, the transmitter element on one side of the line has to suppress, from time to time, a STOP bit in the line transmission. On the other side, the receiver must detect the missing STOP bits in the received data stream and insert a shorter STOP bit in the data transferred to the DTE. Traditionally, the V14 function is achieved by means of complex divider circuits providing from time to time a shorter clock pulse corresponding to a shorter STOP bit that is to be transmitted to the DTE.
Finally, it is highly desirable in modern DCEs to support advanced functions such as data multiplexing on the DTE or error correcting procedures according to the CCITT V42 Recommendations.
As a result, it clearly appears that new functions are continuously added to modern DCEs, thus entailing an on-going sophistication of the timing arrangement circuits. The sophistication of the time arrangement circuits in recent modems have lead to a large multiplication and use of hardware components such as switches, multiplexers, dividers which inevitably increases the cost of the DCE equipment. Moreover, the use of traditional timing arrangement circuits and the large number of hardware components and dividers circuits therein included substantially limit the adaptability of the DCE modem to the new functions that are likely to be requested in the future.